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| System | : | Linux MiraNet 3.0.0-14-generic-pae #23-Ubuntu SMP Mon Nov 21 22:07:10 UTC 2011 i686 |
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| Software | : | Apache. PHP/5.3.6-13ubuntu3.10 |
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| ID | : | uid=65534(nobody) gid=65534(nogroup) groups=65534(nogroup)
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| Safe Mode | : | OFF |
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| Open_Basedir | : | OFF |
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| Freespace | : | 20.2 GB of 70.42 GB (28.68%) |
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MySQL: ON MSSQL: OFF Oracle: OFF PostgreSQL: OFF Curl: OFF Sockets: ON Fetch: OFF Wget: ON Perl: ON |
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Disabled Functions: pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,
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[ System Info ]
[ Processes ]
[ SQL Manager ]
[ Eval ]
[ Encoder ]
[ Mailer ]
[ Back Connection ]
[ Backdoor Server ]
[ Kernel Exploit Search ]
[ MD5 Decrypter ]
[ Reverse IP ]
[ Kill Shell ]
[ FTP Brute-Force ]
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/
usr/
src/
linux-headers-3.0.0-14/
arch/
mn10300/
proc-mn103e010/
include/
proc/
- drwxr-xr-x
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Viewing file:  cache.h (1.65 KB) -rw-r--r--Select action/file-type:  ( +) |  ( +) |  ( +) | Code ( +) | Session ( +) |  ( +) | SDB ( +) |  ( +) |  ( +) |  ( +) |  ( +) |  ( +) |
/* MN103E010 Cache specification
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_PROC_CACHE_H
#define _ASM_PROC_CACHE_H
/* L1 cache */
#define L1_CACHE_NWAYS 4 /* number of ways in caches */
#define L1_CACHE_NENTRIES 256 /* number of entries in each way */
#define L1_CACHE_BYTES 16 /* bytes per entry */
#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */
#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */
#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */
#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY)
/*
* specification of the interval between interrupt checking intervals whilst
* managing the cache with the interrupts disabled
*/
#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
/*
* The size of range at which it becomes more economical to just flush the
* whole cache rather than trying to flush the specified range.
*/
#define MN10300_DCACHE_FLUSH_BORDER \
+(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
#define MN10300_DCACHE_FLUSH_INV_BORDER \
+(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
#endif /* _ASM_PROC_CACHE_H */
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