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| System | : | Linux MiraNet 3.0.0-14-generic-pae #23-Ubuntu SMP Mon Nov 21 22:07:10 UTC 2011 i686 |
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| Software | : | Apache. PHP/5.3.6-13ubuntu3.10 |
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| ID | : | uid=65534(nobody) gid=65534(nogroup) groups=65534(nogroup)
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| Safe Mode | : | OFF |
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| Open_Basedir | : | OFF |
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| Freespace | : | 22.59 GB of 70.42 GB (32.08%) |
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MySQL: ON MSSQL: OFF Oracle: OFF PostgreSQL: OFF Curl: OFF Sockets: ON Fetch: OFF Wget: ON Perl: ON |
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Disabled Functions: pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,
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[ System Info ]
[ Processes ]
[ SQL Manager ]
[ Eval ]
[ Encoder ]
[ Mailer ]
[ Back Connection ]
[ Backdoor Server ]
[ Kernel Exploit Search ]
[ MD5 Decrypter ]
[ Reverse IP ]
[ Kill Shell ]
[ FTP Brute-Force ]
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/
usr/
src/
linux-headers-3.0.0-14/
arch/
mn10300/
unit-asb2364/
include/
unit/
- drwxr-xr-x
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Viewing file:  fpga-regs.h (2.04 KB) -rw-r--r--Select action/file-type:  ( +) |  ( +) |  ( +) | Code ( +) | Session ( +) |  ( +) | SDB ( +) |  ( +) |  ( +) |  ( +) |  ( +) |  ( +) |
/* ASB2364 FPGA registers
*/
#ifndef _ASM_UNIT_FPGA_REGS_H
#define _ASM_UNIT_FPGA_REGS_H
#include <asm/cpu-regs.h>
#ifdef __KERNEL__
#define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16)
#define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16)
#define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16)
#define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
#define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16)
#define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0)
#define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1)
#define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2)
#define ASB2364_FPGA_REG_IRQ_USB ASB2364_FPGA_REG_IRQ(3)
#define ASB2364_FPGA_REG_IRQ_FPGA ASB2364_FPGA_REG_IRQ(5)
#define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16)
#define ASB2364_FPGA_REG_MASK_LAN ASB2364_FPGA_REG_MASK(0)
#define ASB2364_FPGA_REG_MASK_UART ASB2364_FPGA_REG_MASK(1)
#define ASB2364_FPGA_REG_MASK_I2C ASB2364_FPGA_REG_MASK(2)
#define ASB2364_FPGA_REG_MASK_USB ASB2364_FPGA_REG_MASK(3)
#define ASB2364_FPGA_REG_MASK_FPGA ASB2364_FPGA_REG_MASK(5)
#define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16)
#define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16)
#define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16)
#define ASB2364_FPGA_REG_CPLD6_SET2 __SYSREG(0xa9002604, u16)
#define ASB2364_FPGA_REG_CPLD7_SET1 __SYSREG(0xa9002700, u16)
#define ASB2364_FPGA_REG_CPLD7_SET2 __SYSREG(0xa9002704, u16)
#define ASB2364_FPGA_REG_CPLD8_SET1 __SYSREG(0xa9002800, u16)
#define ASB2364_FPGA_REG_CPLD8_SET2 __SYSREG(0xa9002804, u16)
#define ASB2364_FPGA_REG_CPLD9_SET1 __SYSREG(0xa9002900, u16)
#define ASB2364_FPGA_REG_CPLD9_SET2 __SYSREG(0xa9002904, u16)
#define ASB2364_FPGA_REG_CPLD10_SET1 __SYSREG(0xa9002a00, u16)
#define ASB2364_FPGA_REG_CPLD10_SET2 __SYSREG(0xa9002a04, u16)
#define SyncExBus() \
do { \
unsigned short w; \
w = *(volatile short *)0xa9000000; \
} while (0)
#endif /* __KERNEL__ */
#endif /* _ASM_UNIT_FPGA_REGS_H */
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